*68070 *16/32 bit highly integrated microprocessor scc68070 *philips *19900124/wjvg addresses relative to 80000000 *external interrupts controller 1000 latched interrupt priority register (lir) rw 1....... reset pending interrupt 1 rw .nnn.... interrupt 1 level/off rw ....1... reset pending interrupt 2 rw .....nnn interrupt 2 level/off *iic 2001 iic data register (idr) 2003 iic address register (iar) 2005 iic status register (isr) rw 1....... master mode (mst) rw .1...... transmitter (trx) rw ..1..... bus busy (bb) rw ...0.... pending interrupt (pin) rw ....1... arbitration lost (al) rw .....1.. addressed as slave (aas) rw ......1. address zero (ad0) rw .......1 last received bit (lrb) 2007 iic control register (icr) r .1...... selected (sel) rw ....1... enable iic bus (eso) rw .....1.. acknowledge (ack) 2009 iic clock control register (icc) rw ...nnnnn clock divisor illegal, 78, 90, 102, 126, 150, 174, 198, 246, 294, 342, 390, 486, 582, 678, 774, 966, 1158,1350,1542,1926,2310, 2694, 3078, 3846, 4614,5382,6150,7686,9222,10758,12294 scl=19.6608 MHz/2/divisor, maximum clock frequency may be 100 kHz *uart, subset of 2641, 2661, 2691 2011 uart mode register (umr) rw 00...... normal mode rw 01...... auto echo rw 10...... local loopback rw 11...... remote loopback rw ..1..... not used rw ...1.... cstn controls txd rw ....1... parity enable rw .....1.. even parity rw ......1. two/one stopbit(s) rw .......1 8/7 data bits 2013 uart status register (usr) rw 1....... break received rw .1...... framing error rw ..1..... parity error rw ...1.... overrun error rw ....1... tx empty rw .....1.. tx ready rw ......1. not used rw .......1 rx ready 2015 uart clock select register (ucs) rw 1....... external clock source (0 after reset) rw .nnn.... 75,150,300,1200,2400,4800,9600,19200 baud receive (20 MHz) rw ....1... not used rw .....nnn 75,150,300,1200,2400,4800,9600,19200 baud transmit (20 MHz) 2017 uart command register (ucr) rw 1....... not used rw .00n.... no command rw .010.... reset receiver rw .011.... reset transmitter rw .100.... reset error status rw .101.... start break rw .111.... stop break rw ....00.. illegal rw ....01.. enable txd control rw ....10.. disable txd control rw ....11.. illegal rw ......00 illegal rw ......01 enable rxd control rw ......10 disable rxd control rw ......11 illegal 2019 uart transmit holding register (uth) 201b uart receive holding register (urh) *timer 2020 timer status register (tsr) rw 1....... timer 0 overflow rw .1...... timer 1 match rw ..1..... timer 1 capture rw ...1.... timer 1 overflow rw ....1... timer 2 match rw .....1.. timer 2 capture rw ......1. timer 2 overflow 2021 timer control register (tcr) rw 00...... timer 1 input inhibited rw 01...... timer 1 low to high transitions will be monitored rw 10...... timer 1 high to low transitions will be monitored rw 11...... timer 1 any transitions will be monitored rw ..00.... timer 1 inhibited rw ..01.... timer 1 match mode rw ..10.... timer 1 capture mode rw ..11.... timer 1 event counter mode rw ....ee.. timer 2 events idem rw ......mm timer 2 modes idem 2022 reload register high (rrh) 2023 reload register low (rrl) 2024 timer 0 high (t0h) 2025 timer 0 low (t0l) 2026 timer 1 high (t1h) 2027 timer 1 low (t1l) 2028 timer 2 high (t2h) 2029 timer 2 low (t2l) *internal interrupts controller 2045 peripheral interrupt control register 1 (picr1) rw 1....... reset pending iic interrupts rw .nnn.... iic interrupt level/off rw ....1... reset pending timer interrupts rw .....nnn timer interrupt level/off 2047 peripheral interrupt control register 2 (picr2) rw 1....... reset pending uart rx interrupts rw .nnn.... uart rx interrupt level/off rw ....1... reset pending uart tx interrupts rw .....nnn uart tx interrupt level/off *dma controller, compatible with 68430,68440,68450 4000 channel status register channel 1 (csr) rw 1....... operation complete rw .0...... not used rw ..1..... normal device termination rw ...1.... error rw ....1... channel active rw .....001 not used 4001 channel error register channel 1 (cer) rw 000..... not used rw ...00000 no error rw ...00010 timing error rw ...01001 bus error memory address rw ...01010 bus error device address rw ...10001 software abort 4004 device control register channel 1 (dcr) rw 1....... cycle steal/burst mode rw .0...... not used rw ..00.... 68000 device rw ..01.... reserved rw ..10.... reserved rw ..11.... ack/rdy device (this only for channel 1) rw ..001... 16/8 bit port rw .....000 not used 4005 operation control register channel 1 (ocr) rw 1....... device to memory/memory to device rw .0...... not used rw ..00.... byte operand rw ..01.... word operand rw ..1x.... reserved rw ....0010 not used 4006 sequence control register channel 1 (scr) rw 0000.... not used rw ....00.. memory address no change rw ....01.. memory address count up (this only for channel 1) rw ....10.. reserved rw ......00 device address no change rw ......01 device address count up (this only for channel 1) rw ......10 reserved 4007 channel control register channel 1 (ccr) rw 1....... start rw .00..... not used rw ...1.... software abort rw ....1... interrupt enable rw .....nnn interrupt priority level/off 400a memory transfer counter high channel 1 (mtch) 400b memory transfer counter low channel 1 (mtcl) 400c memory address counter high channel 1 (mach) 400d memory address counter middle high channel 1 (macmh) 400e memory address counter middle low channel 1 (macml) 400f memory address counter low channel 1 (macl) 402d channel priority register channel 1 (cpr) rw 00000000 no function (included for compatibility reasons) *dma, channel 2, see channel 1 4040 channel status register channel 2 (csr) 4041 channel error register channel 2 (cer) 4044 device control register channel 2 (dcr) 4045 operation control register channel 2 (ocr) 4046 sequence control register channel 2 (scr) 4047 channel control register channel 2 (ccr) 404a memory transfer counter high channel 2 (mtch) 404b memory transfer counter low channel 2 (mtcl) 404c memory address counter high channel 2 (mach) 404d memory address counter middle high channel 2 (macmh) 404e memory address counter middle low channel 2 (macml) 404f memory address counter low channel 2 (macl) 4054 device address counter high (dach) 4054 device address counter middle high (dacmh) 4054 device address counter middle low (dacml) 4054 device address counter low (dacl) 406d channel priority register channel 2 (cpr) rw 00000001 no function (included for compatibility reasons) *memory management unit *downward compatible with 68910, 68920 (in contiguous segment mode) 8000 mmu status register (msr) rw 1....... not present error rw .1...... stack segment rw ..1..... length violation rw ...1.... access error rw ....1... supervisor bit of violated descriptor rw .....1.. execute bit of violated descriptor rw ......1. read bit of violated descriptor rw .......1 write bit of violated descriptor 8001 mmu control register (mcr) rw 1....... enable mmu rw .1...... 128/8 segments 8040 descriptor 0 80x0 segment attributes (sah,sal) rw 1....... ........ valid and present, not used, for use in memory rw .1...... ........ supervisor permission required rw ..1..... ........ segment is executable rw ...1.... ........ segment is readable rw ....1... ........ segment is writable rw .....xxx x.xxxxxx not used rw ........ .1...... stack segment 80x2 segment length (slh,sll) rw xxxxx... ........ not used rw .....nnn nnnnnnnn used (-1) 80x4 segment number (x,snr) rw xxxxxxxx ........ not used rw ........ 1....... descriptor valid rw ........ .nnnnnnn segment number (left justified) 80x6 segment base address (sbh,sbl) rw xx...... ........ not used rw ..nnnnnn nnnnnnnn used 80x7 segment base address low (sbl) 8048 descriptor 1 8050 descriptor 2 8058 descriptor 3 8060 descriptor 4 8068 descriptor 5 8070 descriptor 6 8078 descriptor 7 *end