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[FastForward Newsletter]

February 1995 :

FastForward Sony Taps LSI Logic for PlayStation Video Game CPU Chip

Be sure to answer the questions at the end of this article.

LSI Logic's job: integrate a 32-bit RISC microprocessor, a JPEG video decoder and a 3D graphics engine on a single chip, as well as deliver prototypes in record time.

The stakes were high: a share of the $12 billion home video game market. Sony Corporation, the world-class supplier of entertainment systems ranging from giant projection TV sets to tiny Walk-man cassette players, knew that the only way to crack an established market was to bring something new to the game. They reasoned that cartridge-based video games had run their course. So had 16-bit game engines.

Sony concluded that the future of video games lies with proven CD-ROM technology, 32-bit game engines driven by powerful RISC microprocessors, photographic-quality image compression technology, and high-resolution, fast graphics. Sony had designed a system that met those specifications: the Sony PlayStation. With its television-quality 3D graphics and instant reaction to player commands, Sony's new system outperformed everything on the market.

The problem was the game system electronics consisted of several printed circuit boards that contained hundreds of ICs and occupied several shelves of an electronics rack. Clearly, it couldn't go to market in that configuration. To be marketable, the PlayStation had to be shrunk to a size that a child could handle and had to be introduced with a retail price in the $300-$500 range. It had to be delivered in Japan by Christmas of 1994 and in the U.S. and Europe in mid-1995.

Single-Chip Solution Needed

To meet the size, performance and price constraints, the PlayStation CPU had to fit on a single chip. That meant integrating a 32-bit MIPS RISC microprocessor, a 3D graphics engine and a JPEG decoder, together with the necessary glue logic and memory blocks.

It was a tall order. And given the challenge of the task at hand, the success of the program depended on the choice of an ASIC partner.

Sony Computer Entertainment selected LSI Logic as that ASIC partner. It was spring of 1993 when a team of Sony and LSI Logic engineers went to work on the task. First prototypes had to be delivered by the end of the year.

LSI Logic's CoreWare® methodology could put the entire PlayStation CPU on a single chip. Other alternatives would need at least two chips. The CoreWare library included a MIPS R3000 core and a JPEG core that would be used in the PlayStation CPU chip with only minor modifications. And LSI Logic's state-of-the-art 0.5-micron fabrication facility had the capacity to manufacture production chips in the volume that Sony needed.

That left the graphics engine, DMA controller, I/O and bus controllers as the primary development tasks. LSI Logic's applications engineers, both in the U.S. and in Japan, had the experience necessary to quickly generate these circuits to meet Sony's specifications.

PlayStation Architecture

With an operating speed of 34 MHz, the Sony PlayStation is capable of executing over 500 million instructions per second (MIPS), rivaling engineering workstations in raw computer power. The PlayStation CPU is an excellent example of system-on-a-chip integration. It integrates a MIPS R3000 RISC core, 4 KBytes of instruction cache, 1 KBytes of data cache, a motion JPEG decode engine, a 3D graphics transformation engine (GTE ), a 7-channel DMA controller, a DRAM controller, a cache controller, triple 16-bit counter/timers, 2 serial I/O ports and a register file—all onto one chip.

The CPU design employs a 32-bit internal bus for high-speed inter-chip communications, and a 16-bit external bus for communication with slower peripheral devices.

A major element that differentiates Sony's PlayStation from the competition is the graphics transformation engine, a proprietary Sony design. It acts as a coprocessor to the R3000 MIPS CPU, operates on a combination of CPU and GTE instruction sets, and shares the instruction and data buses with the CPU. It handles matrix calculations, coordinate transformations, perspective projections, lighting calculations, and fixed-point calculations, all at speeds far higher than could be performed by the CPU alone.

The motion JPEG decoder engine processes graphics files that have been compressed using the JPEG compression algorithm. The JPEG engine, part of LSI Logic's CoreWare library, performs inverse discrete cosine transform (IDCT) functions, IDCT matrix coefficient set-up and IQ matrix coefficient set-up, supporting both 16-bit and 24-bit color. It uses DMA channels to read from CD-ROM and to write to DRAM.

The JPEG decoder engine is based on LSI Logic's JPEG core. Modifications to the standard core involve the removal of some JPEG functions that are not used in the PlayStation, thus reducing the size of the core and the over-all size of the CPU chip.

PlayStation System Block Diagram

Developed on Schedule

The development team consisted of engineering teams in the U.S. and in Japan. Each team included both LSI Logic and Sony engineers, with some LSI Logic engineers working at Sony and some Sony engineers working at LSI Logic.

Sony's engineers provided the systems expertise, defining the specifications that LSI Logic's team then implemented in silicon. Development proceeded rapidly, and first prototypes were delivered within schedule. First prototypes were functional, allowing the design teams to concentrate on refining the design rather than on fixing design flaws and allowing game title development to commence early.

As a result of the team effort, the PlayStation CPU was designed and fabricated to Sony's exact specifications and fine-tuned to the PlayStation application in record time.

500K Process

The PlayStation CPU chip is one of the first system-level designs to be fabricated in LSI Logic's 0.5-micron 500K process technology. Production chips were fabricated to meet Sony's product introduction in time for Christmas and in the volume needed to meet Sony's delivery schedule.

Proven Concept

Despite its complexity, the PlayStation CPU chip does not strain the integration capability of the 500K process, nor does it tax the 500K's performance capabilities. Employing LSI Logic's CoreWare® methodology, Sony and LSI Logic engineers were able to create a design in months that would have been inconceivable just two years ago. The result demonstrates the benefits of the CoreWare methodology for large designs.

But equally significant, the PlayStation project highlights the concept of a partnership between customer and vendor. Neither Sony nor LSI Logic could have created this product alone. Sony provided the systems expertise and market knowledge and LSI Logic provided the implementation expertise.

Other companies that have complex programs should take notice. LSI Logic is ready to help.

For more information about this partnership, please read the story in the 1994 Annual Report.

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